Que: (5).
A system uses 1 KB pages and byte-addressable memory. What are the page number and offset for logical address 2500, assuming zero-based addressing?
Que: (6).
A system has four free memory holes of 10 KB, 15 KB, 20 KB and 25 KB. A process requires 60 KB of contiguous memory. Assuming no other constraints, what is the minimum total free memory that must be available before compaction can satisfy the request?
Que: (9).
Free memory blocks are 100 KB, 500 KB, 200 KB, 300 KB and 600 KB, in that order. Using first-fit allocation, which block is allocated to a process requesting 212 KB?
Que: (10).
A system has 100 KB of total free memory distributed among several holes. A process requests 80 KB of contiguous memory, but the largest free hole is only 60 KB. Which conclusion is correct?
Que: (11).
Secondary memory is the long-term store for programs and data, while main memory holds programs and data currently in use. What kind of organization is this?
Que: (14).
A CPU frequently accesses the same instructions and nearby memory locations. Which principle explains why cache memory can improve performance?
Que: (16).
A computer runs a program whose total virtual address space exceeds the available physical RAM. Which mechanism can allow the program to run by keeping only parts of it in RAM?
Que: (17).
A system has a cache hit ratio of 90%. Cache access time is 5 ns and the additional time required to access main memory after a cache miss is 80 ns. Assuming the miss penalty is additional to cache access time, what is the average memory access time?
Que: (18).
A hard disk rotates at 7200 revolutions per minute. Assuming a uniformly distributed rotational position, what is the average rotational latency?
Que: (19).
A file system allocates storage in blocks of 4 KB. A file contains 10000 bytes and requires an integer number of blocks. Assuming 1 KB = 1024 bytes and no compression, how many bytes are allocated, and how much space is unused in the final block?
Que: (20).
A server stores critical data on two disks and maintains identical copies of the data on both disks. If either disk fails, the other can continue providing the stored data. Which RAID level describes this arrangement?
Que: (28).
A conditional branch instruction executes only when the zero flag is set. Which information must the control unit use to determine whether to take the branch?
Que: (29).
In a pipelined processor, an instruction needs a result that has not yet been produced by an earlier instruction. If forwarding cannot resolve the dependency, what should the control unit typically do?
Que: (30).
A simple processor uses a four-stage instruction cycle. Each stage requires one clock cycle, and there are no stalls or overlapping operations. How many clock cycles are required to complete 25 instructions?
Que: (37).
A device produces data at 20 MB/s, while a receiver consumes data at 12 MB/s. If production continues at these constant rates for 5 seconds without the receiver catching up, how much buffer capacity is required to accommodate the accumulated data?
Que: (38).
A producer generates data faster than a consumer can process it. The buffer has a fixed capacity and eventually becomes full. What is the most appropriate general conclusion?
Que: (39).
A 32-bit bus transfers one data word per clock cycle at a clock frequency of 100 MHz. Assuming one transfer per cycle and ignoring overhead, what is its theoretical data transfer rate?
Que: (40).
A system transfers data in blocks of 8 KB. Each block takes 2 ms to transfer and 3 ms to process. Assuming transfer and processing use separate resources, double buffering is used, and startup and shutdown overhead are ignored, what is the approximate steady-state throughput?
Que: (44).
A processor has a 16-bit address bus and uses the entire address space for memory-mapped addressing. How many distinct byte addresses can it generate?
Que: (46).
A system uses memory-mapped I/O. An address generated by the CPU falls within the address range assigned to a device register. What should the address-decoding hardware do?
Que: (47).
A system designer wants to reserve the full range of addresses for memory and access peripheral devices through a separate port address space. Which I/O organization best meets this requirement?
Que: (49).
A byte-addressable processor has a 20-bit address space. If 16 KiB of that address space is reserved for memory-mapped I/O registers, how much address space remains for other uses?
Que: (50).
A program reads a device status register using an ordinary load instruction, but the register is accessed through a special I/O instruction on the processor. Which is the most likely explanation?
Que: (60).
A system uses polling to check whether an output device can accept another character. Which status condition should the CPU typically wait for?
Que: (70).
A control unit must coordinate register loading, ALU operation, and memory access during an instruction. What determines when these micro-operations occur?
