When does a negative level triggered flip-flop in Digital Electronics changes its state?

Asked In: BPSC TRE 3.0

Options

  • A. When the clock is Negative
  • B. When the clock is Positive
  • C. When the inputs are all zero
  • D. More than one of the above
  • E. None of the above

Correct Answer (Detailed Explanation is Below)

A. When the clock is Negative

Detailed Explanation

Explanation: A negative level-triggered flip-flop (or level-sensitive latch) responds during the LOW level of the clock signal. It is enabled when the clock is 0. Note: This is different from a negative-edge-triggered flip-flop, which changes state at the falling edge of the clock.
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BPSC Tre 4.0 Digtial Electronics Quiz Practice Set 1

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